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pll frequency synthesizer adf4107 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2003C2007 analog devices, inc. all rights reserved. features 7.0 ghz bandwidth 2.7 v to 3.3 v power supply separate charge pump supply (v p ) allows extended tuning voltage in 3 v systems programmable dual-modulus prescaler 8/9, 16/17, 32/33, 64/65 programmable charge pump currents programmable antibacklash pulse width 3-wire serial interface analog and digital lock detect hardware and software power-down mode applications broadband wireless access satellite systems instrumentation wireless lans base stations for wireless radio general description the adf4107 frequency synthesizer can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. it consists of a low noise digital pfd (phase frequency detector), a precision charge pump, a programmable reference divider, programmable a and b counters, and a dual-modulus prescaler (p/p + 1). the a (6-bit) and b (13-bit) counters, in conjunction with the dual-modulus prescaler (p/p + 1), implement an n divider (n = bp + a). in addition, the 14-bit reference counter (r counter), allows selectable ref in frequencies at the pfd input. a complete pll (phase-locked loop) can be implemented if the synthesizer is used with an external loop filter and vco (voltage controlled oscillator). its very high bandwidth means that frequency doublers can be eliminated in many high frequency systems, simplifying system architecture and reducing cost. functional block diagram 03338-001 clk data le ref in rf in a rf in b 24-bit input register sd out a v dd dv dd ce agnd dgnd 14-bit r counter r counter latch 22 14 function latch a, b counter latch from function latch prescaler p/p + 1 n = bp + a load load 13-bit b counter 6-bit a counter 6 19 13 m3 m2 m1 mux sd out av dd high z muxout cpgnd r set v p cp phase frequency detector lock detect reference charge pump current setting 1 adf4107 cpi3 cpi2 cpi1 cpi6 cpi5 cpi4 current setting 2 figure 1.
adf4107 rev. a | page 2 of 20 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 timing characteristics ................................................................ 4 absolute maximum ratings............................................................ 5 esd caution.................................................................................. 5 pin configurations and function descriptions ........................... 6 typical performance characteristics ............................................. 7 functional description .................................................................... 9 reference input stage................................................................... 9 rf input stage............................................................................... 9 prescaler (p/p + 1)........................................................................ 9 a and b counters ......................................................................... 9 r counter ...................................................................................... 9 phase frequency detector and charge pump...........................9 muxout and lock detect...................................................... 10 input shift register .................................................................... 10 latch summary........................................................................... 11 reference counter latch map.................................................. 12 ab counter latch map ............................................................. 13 function latch map................................................................... 14 initialization latch map ............................................................ 15 function latch............................................................................ 16 initialization latch ..................................................................... 17 applications..................................................................................... 18 local oscillator for lmds base station transmitter............ 18 interfacing ................................................................................... 19 pcb design guidelines for chip scale package .................... 19 outline dimensions ....................................................................... 20 ordering guide .......................................................................... 20 revision history 4/07rev. 0 to rev. a updated format..................................................................universal changes to ref in characteristics section..................................... 3 changes to noise characteristics section..................................... 4 changes to absolute maximum ratings section......................... 5 changes to figure 23...................................................................... 12 changes to ordering guide .......................................................... 20 5/03revision 0: initial version
adf4107 rev. a | page 3 of 20 specifications av dd = dv dd = 3 v 10%, av dd v p 5.5 v, agnd = dgnd = cpgnd = 0 v, r set = 5.1 k, dbm referred to 50 , t a = t max to t min , unless otherwise noted. table 1. parameter b version 1 b chips 2 (typ) unit test conditions/comments rf characteristics rf input frequency (rf in ) 3 1.0/7.0 1.0/7.0 ghz min/max see figure 18 for input circuit rf input sensitivity C5/+5 C5/+5 dbm min/max maximum allowable prescaler output frequency 4 300 300 mhz max ref in characteristics ref in input frequency 20/250 20/250 mhz min/max for f < 20 mhz, ensure slew rate >50 v/s ref in input sensitivity 5 0.8/v dd 0.8/v dd v p-p min/max biased at av dd /2 6 ref in input capacitance 10 10 pf max ref in input current 100 100 a max phase detector phase detector frequency 7 104 104 mhz max abp = 0,0 (2.9 ns antibacklash pulse width) charge pump programmable; see figure 25 i cp sink/source high value 5 5 ma typ with r set = 5.1 k low value 625 625 a typ absolute accuracy 2.5 2.5 % typ with r set = 5.1 k r set range 3.0 to 11 3.0 to 11 k typ see figure 25 i cp three-state leakage 1 1 na typ sink and source current matching 2 2 % typ 0.5 v v cp v p ? 0.5 v i cp vs. v cp 1.5 1.5 % typ 0.5 v v cp v p ? 0.5 v i cp vs. temperature 2 2 % typ v cp = v p /2 logic inputs v ih , input high voltage 1.4 1.4 v min v il , input low voltage 0.6 0.6 v max i inh , i inl , input current 1 1 a max c in , input capacitance 10 10 pf max logic outputs v oh , output high voltage 1.4 1.4 v min open-drain output chosen; 1 k pull-up resistor to 1.8 v v oh , output high voltage v dd ? 0.4 v dd ? 0.4 v min cmos output chosen i oh 100 100 a max v ol , output low voltage 0.4 0.4 v max i ol = 500 a power supplies av dd 2.7/3.3 2.7/3.3 v min/v max dv dd av dd av dd v p av dd /5.5 av dd /5.5 v min/v max av dd v p 5.5 v i dd 8 (ai dd + di dd ) 17 15 ma max 15 ma typ i p 0.4 0.4 ma max t a = 25c power-down mode 9 (ai dd + di dd ) 10 10 a typ
adf4107 rev. a | page 4 of 20 parameter b version 1 b chips 2 (typ) unit test conditions/comments noise characteristics adf4107 normalized phase noise floor 10 ?219 ?219 dbc/hz typ phase noise performance 11 @ vco output 900 mhz output 12 ?93 ?93 dbc/hz typ @ 1 khz offset and 200 khz pfd frequency 6400 mhz output 13 ?76 ?76 dbc/hz typ @ 1 khz offset and 200 khz pfd frequency 6400 mhz output 14 ?83 ?83 dbc/hz typ @ 1 khz offset and 1 mhz pfd frequency spurious signals 900 mhz output 12 ?90/?92 ?90/?92 dbc typ @ 200 kh z/400 khz and 200 khz pfd frequency 6400 mhz output 13 ?65/?70 ?65/?70 dbc typ @ 200 kh z/400 khz and 200 khz pfd frequency 6400 mhz output 14 ?70/?75 ?70/?75 dbc typ @ 1 mh z/2 mhz and 1 mhz pfd frequency 1 operating temperature range (b version) is ?40c to +85c. 2 the b chip specifications are given as typical values. 3 use a square wave for lower frequencies, below the minimum stated. 4 this is the maximum operating frequency of the cmos counters. the prescaler value should be chosen to ensure that the rf input is divided down to a frequency that is less than this value. 5 av dd = dv dd = 3 v. 6 ac-coupling ensures av dd /2 bias. 7 guaranteed by design. sample tested to ensure compliance. 8 t a = 25c; av dd = dv dd = 3 v; p = 32; rf in = 7.0 ghz. 9 t a = 25c; av dd = dv dd = 3.3 v; r = 16,383; a = 63; b = 891; p = 32; rf in = 7.0 ghz. 10 the synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the vco and subtracting 2 0logn (where n is the n divider value) and 10log(f pfd ). pn synth = pn tot ? 20logn ?10logf pfd . 11 the phase noise is measured with the eval-adf4107e b1 evaluation board and the hp8562e spec trum analyzer. the spectrum analyzer provides the ref in for the synthesizer (f refout = 10 mhz @ 0 dbm). 12 f refin = 10 mhz; f pfd = 200 khz; offset frequency = 1 khz; f rf = 900 mhz; n = 4500; loop bw = 20 khz. 13 f refin = 10 mhz; f pfd = 200 khz; offset frequency = 1 khz; f rf = 6400 mhz; n = 32,000; loop bw = 20 khz. 14 f refin = 10 mhz; f pfd = 1 mhz; offset frequency = 1 khz; f rf = 6400 mhz; n = 6400; loop bw = 100 khz. timing characteristics av dd = dv dd = 3 v 10%, av dd v p 5.5 v, agnd = dgnd = cpgnd = 0 v, r set = 5.1 k, dbm referred to 50 , t a = t max to t min , unless otherwise noted. 1 table 2. parameter limit 2 (b version) unit test conditions/comments t 1 10 ns min data to clock setup time t 2 10 ns min data to clock hold time t 3 25 ns min clock high duration t 4 25 ns min clock low duration t 5 10 ns min clock to le setup time t 6 20 ns min le pulse width 1 guaranteed by design but not production tested. 2 operating temperature range (b version) is ?40c to +85c. 03338-002 clock db22 db2 data le t 1 le db23 (msb) t 2 db1 (control bit c2) db0 (lsb) (control bit c1) t 3 t 4 t 6 t 5 figure 2. timing diagram
adf4107 rev. a | page 5 of 20 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating av dd to gnd 1 ?0.3 v to +3.6 v av dd to dv dd ?0.3 v to +0.3 v v p to gnd ?0.3 v to +5.8 v v p to av dd ?0.3 v to +5.8 v digital i/o voltage to gnd ?0.3 v to v dd + 0.3 v analog i/o voltage to gnd ?0.3 v to v p + 0.3 v ref in , rf in a, rf in b to gnd ?0.3 v to v dd + 0.3 v operating temperature range industrial (b version) ?40c to +85c storage temperature range ?65c to +125c maximum junction temperature 150c tssop ja thermal impedance 112c/w lfcsp ja thermal impedance (paddle soldered) 30.4c/w reflow soldering peak temperature 260c time at peak temperature 40 sec transistor count cmos 6425 bipolar 303 1 gnd = agnd = dgnd = 0 v. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. this device is a high performance rf integrated circuit with an esd rating of <2 kv, and it is esd sensitive. proper precautions should be taken for handling and assembly. esd caution
adf4107 rev. a | page 6 of 20 pin configurations and function descriptions 03338-003 r set cp cpgnd agnd 1 2 3 4 5 6 7 8 rf in b rf in a av dd ref in muxout le data clk ce dgnd 16 15 14 13 12 11 10 9 v p dv dd top view (not to scale) adf4107 notes: 1. transistor count 6425 (cmos), 303 (bipolar). figure 3. pin configuration, tssop 03338-004 15 muxout 14 le 13 data 12 clk cpgnd 1 agnd 2 agnd 3 20 cp 11 ce 6 7 8 dgnd 9 dgnd 10 19 18 17 16 rf in b 4 rf in a 5 r set v p dv dd dv dd pin 1 indicator top view adf4107 av dd av dd ref in notes: 1. transistor count 6425 (cmos), 303 (bipolar). figure 4. pin configuration, lfcsp table 4. pin function descriptions pin no. tssop lfcsp mnemonic description 1 19 r set connecting a resistor between this pin and cpgnd se ts the maximum charge pump output current. the nominal voltage potential at the r set pin is 0.66 v. the relationship between i cp and r set is set maxcp r i = so, with r set = 5.1 k, i cp max = 5 ma. 2 20 cp charge pump output. when enabled, this pin provides i cp to the external loop filter, which in turn drives the external vco. 3 1 cpgnd charge pump ground. this is th e ground return path for the charge pump. 4 2, 3 agnd analog ground. this is the ground return path of the prescaler. 5 4 rf in b complementary input to the rf prescaler. this point must be decoupled to the ground plane with a small bypass capacitor, typically 100 pf. see figure 18 . 6 5 rf in a input to the rf prescaler. this small signal input is ac-coupled to the external vco. 7 6, 7 av dd analog power supply. this voltage may range from 2.7 v to 3.3 v. decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. av dd must be the same value as dv dd . 8 8 ref in reference input. this is a cmos in put with a nominal threshold of v dd /2 and a dc equivalent input resistance of 100 k. see figure 17 . this input can be driven from a ttl or cmos crystal oscillator or it can be ac-coupled. 9 9, 10 dgnd digital ground. 10 11 ce chip enable. a logic low on this pin powers down the device and puts the charge pump output into three- state mode. taking the pin high powers up the device, depending on the status of the power-down bit, f2. 11 12 clk serial clock input. this serial clock is used to clock in the serial data to the registers. the data is latched into the 24-bit shift register on the clk rising ed ge. this input is a high impedance cmos input. 12 13 data serial data input. the serial data is loaded msb first with the two ls bs being the control bits. this input is a high impedance cmos input. 13 14 le load enable, cmos input. when le goes high, the data stored in the shift registers is loaded into one of the four latches, the latch being selected using the control bits. 14 15 muxout this multiplexer output allows either the lock detect, the scaled rf, or the scaled reference frequency to be accessed externally. 15 16, 17 dv dd digital power supply. this may range from 2.7 v to 3. 3 v. decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. dv dd must be the same value as av dd . 16 18 v p charge pump power supply. this voltage should be greater than or equal to v dd . in systems where v dd is 3 v, it can be set to 5 v and used to drive a vco with a tuning range of up to 5 v.
adf4107 rev. a | page 7 of 20 typical performance characteristics 03338-005 figure 5. parameter data for the rf input 0 ?30 ?5 ?10 ?25 ?20 ?15 03338-006 6 5 4 3 2 1 0 rf input frequency (ghz) rf input power (dbm) v dd = 3v v p = 3v t a = +85c t a = ?40c t a = +25c figure 6. input sensitivity 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 03338-007 ?2khz ?1khz 900mhz 1khz 2khz frequency output power (db) v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 200khz loop bandwidth = 20khz res bandwidth = 10hz video bandwidth = 10hz sweep = 1.9 seconds averages = 10 ?93.0dbc/hz ref level = ?14.3dbm figure 7. phase noise (900 mhz, 200 khz, 20 khz) ? 40 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 03338-008 100hz 1mhz frequency offset from 900mhz carrier phase noise (dbc/hz) 10db/div r l = ?40dbc/hz rms noise = 0.36 figure 8. integrated phase noise (900 mhz, 200 khz, 20 khz) 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 03338-009 ?400khz ?200khz 900mhz 200khz 400khz frequency output power (db) ref level = ?14.0dbm v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 200khz loop bandwidth = 20khz res bandwidth = 1khz video bandwidth = 1khz sweep = 2.5 seconds averages = 30 ?91.0dbc/hz figure 9. reference spurs (900 mhz, 200 khz, 20 khz) ?83.5dbc/hz 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 03338-010 ?2khz ?1khz 6400mhz 1khz 2khz frequency output power (db) ref level = ?10dbm v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 1mhz loop bandwidth = 100khz res bandwidth = 10hz video bandwidth = 10hz sweep = 1.9 seconds averages = 10 figure 10. phase noise (6.4 ghz, 1 mhz, 100 khz)
adf4107 rev. a | page 8 of 20 ? 40 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 03338-011 100hz 1mhz frequency offset from 5800mhz carrier phase noise (dbc/hz) 10db/div r l = ?40dbc/hz rms noise = 1.8 figure 11. integrated phase noise (6.4 ghz, 1 mhz, 100 khz) 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 03338-012 ?2khz ?1khz 5800mhz 1khz 2khz frequency (mhz) output power (db) ref level = ?10dbm ?65.0dbc ?66.0dbc v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 1mhz loop bandwidth = 100khz res bandwidth = 1khz video bandwidth = 1khz sweep = 13 seconds averages = 1 figure 12. reference spurs (6.4 ghz, 1 mhz, 100 khz) ? 60 ?100 ?90 ?80 ?70 03338-013 100 ?40 ?20 0 20 40 60 80 temperature (c) phase noise (dbc/hz) v dd = 3v v p = 3v figure 13. phase noise (6.4 ghz, 1 mhz, 100 khz) vs. temperature ? 5 ?105 ?95 ?85 ?75 ?65 ?55 ?45 ?35 ?25 ?15 03338-014 5 01234 tuning voltage (v) first reference spur (dbc) v dd = 3v v p = 5v figure 14. reference spurs vs. v tune (6.4 ghz, 1 mhz, 100 khz) ? 120 ?180 ?170 ?160 ?150 ?140 ?130 03338-015 100m 10k 100k 1m 10m phase detector frequency (hz) phase noise (dbc/hz) v dd = 3v v p = 5v figure 15. phase noise (referred to cp output) vs. pfd frequency ? 6 6 5 4 3 2 1 0 ?1 ?2 ?3 ?4 ?5 03338-016 5.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v cp (v) i cp (ma) v p = 5v i cp settling = 5ma figure 16. charge pump output characteristics
adf4107 rev. a | page 9 of 20 functional description reference input stage the reference input stage is shown in figure 17 . sw1 and sw2 are normally closed switches. sw3 is normally open. when power-down is initiated, sw3 is closed and sw1 and sw2 are opened. this ensures that there is no loading of the ref in pin on power-down. 03338-017 100k ? nc ref in nc no sw1 sw2 buffer sw3 to r counte r power-down control figure 17. reference input stage rf input stage the rf input stage is shown in figure 18 . it is followed by a 2-stage limiting amplifier to generate the cml clock levels needed for the prescaler. 03338-018 500 ? 1.6v 500? agnd rf in a rf in b av dd bias generator figure 18. rf input stage prescaler (p/p + 1) the dual-modulus prescaler (p/p + 1), along with the a and b counters, enables the large division ratio, n, to be realized (n = bp + a). the dual-modulus prescaler, operating at cml levels, takes the clock from the rf input stage and divides it down to a manageable frequency for the cmos a and cmos b counters. the prescaler is programmable. it can be set in software to 8/9, 16/17, 32/33, or 64/65. it is based on a synchronous 4/5 core. a minimum divide ratio is possible for fully contiguous output frequencies. this minimum is determined by p, the prescaler value, and is given by: (p 2 ? p). a and b counters the a and b cmos counters combine with the dual-modulus prescaler to allow a wide ranging division ratio in the pll feedback counter. the counters are specified to work when the prescaler output is 300 mhz or less. thus, with an rf input frequency of 4.0 ghz, a prescaler value of 16/17 is valid but a value of 8/9 is not valid. pulse swallow function the a and b counters, in conjunction with the dual-modulus prescaler, make it possible to generate output frequencies that are spaced only by the reference frequency divided by r. the equation for the vco frequency is as follows: r f abpf refin vco uu where: f vco is the output frequency of external voltage controlled oscillator (vco). p is the preset modulus of dual-modulus prescaler (8/9, 16/17). b is the preset divide ratio of binary 13-bit counter (3 to 8191). a is the preset divide ratio of binary 6-bit swallow counter (0 to 63). f refin is the external reference frequency oscillator. load load from rf input stage prescaler p/p + 1 13-bit b counter to pfd 6-bit a counter n divider modulus control n = bp + a 03338-019 figure 19. a and b counters r counter the 14-bit r counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (pfd). division ratios from 1 to 16,383 are allowed. phase frequency detector and charge pump the phase frequency detector (pfd) takes inputs from the r counter and n counter (n = bp + a) and produces an output proportional to the phase and frequency difference between them. figure 20 is a simplified schematic. the pfd includes a programmable delay element that controls the width of the antibacklash pulse. this pulse ensures that there is no dead zone in the pfd transfer function and minimizes phase noise and reference spurs. two bits in the reference counter latch, abp2 and abp1, control the width of the pulse. use of the minimum antibacklash pulse width is not recommended. see figure 23 .
adf4107 rev. a | page 10 of 20 hi hi d1 d2 q1 q2 clr2 cp u1 u2 up down abp2 abp1 cpgnd u3 r divider programmable delay n divider v p charge pump 0 3338-020 clr1 figure 20. pfd simplified sche matic and timing (in lock) muxout and lock detect the output multiplexer on the adf4107 allows the user to access various internal points on the chip. the state of muxout is controlled by m3, m2, and m1 in the function latch. figure 25 shows the full truth table. figure 21 shows the muxout section in block diagram form. lock detect muxout can be programmed for two types of lock detect: digital lock detect and analog lock detect. digital lock detect is active high. when the lock detect precision (ldp) bit in the r counter latch is set to 0, digital lock detect is set high when the phase error on three consecutive phase detector (pd) cycles is less than 15 ns. with ldp set to 1, five consecutive cycles of less than 15 ns are required to set the lock detect. it stays set high until a phase error of greater than 25 ns is detected on any subsequent pd cycle. the n-channel open-drain analog lock detect should be operated with an external pull-up resistor of 10 k nominal. when lock has been detected, this output becomes high with narrow, low going pulses. 0 3338-021 dgnd dv dd control mux analog lock detect digital lock detect r counter output n counter output sdout muxou t figure 21. muxout circuit input shift register the adf4107 digital section includes a 24-bit input shift register, a 14-bit r counter, and a 19-bit n counter, comprising a 6-bit a counter and a 13-bit b counter. data is clocked into the 24-bit shift register on each rising edge of clk. the data is clocked in msb first. data is transferred from the shift register to one of four latches on the rising edge of le. the destination latch is determined by the state of the two control bits (c2, c1) in the shift register. these are the two lsbs, db1 and db0, as shown in the timing diagram of figure 2 . the truth table for these bits is shown in table 5 . figure 22 shows a summary of how the latches are programmed. table 5. c2, c1 truth table control bits c2 c1 data latch 0 0 r counter 0 1 n counter (a and b) 1 0 function latch (including prescaler) 1 1 initialization latch
adf4107 rev. a | page 11 of 20 latch summary db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) r1 r2 r3r4 r5 r6 r7r8r9 r10 r11 r12 r13 r14 abp1 abp2 t1t2 ldp db21 db22 db23 00 x db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) a1 a2 a3a4a5 b1 b2b3b4b5 b6 b7b8b9 b10 b11 b12 b13 a6 db21 db22 db23 g1 xx db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) f1 pd1 m1m2m3 f3 p1p2 cpi1 cpi2 cpi5 cpi6 tc4 pd2 f2 cpi3 cpi4 db21 tc3 tc2 tc1 db22 db23 f4 f5 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 d b 8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (1) f1 pd1 m1m2 m3 f3 p1p2 cpi1 cpi2 cpi5 cpi6 tc4 pd2 f2 cpi3 cpi4 db21 tc3 tc2 tc1 db22 db23 f4f5 reference counter l a tch reserved lock detect precision test mode bits anti- backlash width 14-bit reference counter control bits reserved 13-bit b counter 6-bit a counter control bits n counter latch cp gain function latch prescaler value power- down 2 current setting 2 current setting 1 timer counter control fastlock mode fastlock enable cp three- state pd polarity muxout control power- down 1 counter reset control bits prescaler value power- down 2 current setting 2 current setting 1 timer counter control fastlock mode fastlock enable cp three- state pd polarity muxout control power- down 1 counter reset control bits initialization latch 03338-022 figure 22. latch summary
adf4107 rev. a | page 12 of 20 reference counter latch map ldp 0 1 abp2 abp1 0 0 2.9ns 0 1 1.3ns test mode only. do not use 1 0 6.0ns 1 1 2.9ns r14 r13 r12 .......... r3 r2 r1 0 0 0 .......... 0 0 1 1 0 0 0 .......... 0 1 0 2 0 0 0 .......... 0 1 1 3 0 0 0 .......... 1 0 0 4 . . . .......... . . . . . . . .......... . . . . . . . .......... . . . . 1 1 1 .......... 1 0 0 16380 1 1 1 .......... 1 0 1 16381 1 1 1 .......... 1 1 0 16382 1 1 1 .......... 1 1 1 16383 x = don?t care db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) r1 r2r3 r4 r5r6r7r8r9 r10 r11 r12 r13 r14 abp1 abp2 t1t2 ldp db21 db22 db23 00 x reserved lock detect precision test mode bits anti- backlash width 14-bit reference counter control bits divide ratio antibacklash pulse width test mode bits should be set to 00 for normal operation. operation three consecutive cycles of phase delay less than 15ns must occur before lock detect is set. five consecutive cycles of phase delay less than 15ns must occur before lock detect is set. both of these bits must be set to 0 for normal operation. 03338-023 figure 23. reference counter latch map
adf4107 rev. a | page 13 of 20 ab counter latch map db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) a1 a2a3 a4 a5 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 a6 db21 db22 db23 g1 00 0 1 1 0 f4 (function latch) fastlock enable 11 a6 a5 .......... a2 a1 0 0 .......... 0 0 0 0 0 .......... 0 1 1 0 0 .......... 1 0 2 0 0 .......... 1 1 3 . . .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... 0 0 60 1 1 .......... 0 1 61 1 1 .......... 1 0 62 1 1 .......... 1 1 63 xx b13 b12 b11 b3 b2 b1 0 0 0 .......... 0 0 0 0 0 0 .......... 0 0 1 0 0 0 .......... 0 1 0 0 0 0 .......... 0 1 1 3 . . . .......... . . . . . . . .......... . . . . . . . .......... . . . . 1 1 1 .......... 1 0 0 8188 1 1 1 .......... 1 0 1 8189 1 1 1 .......... 1 1 0 8190 1 1 1 .......... 1 1 1 8191 x = don?t care reserved 13-bit b counter 6-bit a counter control bits cp gain a counter divide ratio b counter divide ratio not allowed not allowed not allowed these bits are not used by the device and are don't care bits. operation cp gain charge pump current setting 1 is permanently used. charge pump current setting 2 is permanently used. charge pump current setting 1 is used. charge pump current is switched to setting 2. the time spent in setting 2 is dependent on which fastlock mode is used. see function latch description. n = bp + a, p is prescaler value set in the function latch. b must be greater than or equal to a. for continuously adjacent values of (n f ref ), at the output, n min is (p 2 ? p). 0 3338-024 figure 24. ab counter latch map
adf4107 rev. a | page 14 of 20 function latch map p2 p1 00 8/9 0 1 16/17 1 0 32/33 1 1 64/65 pd2 pd1 mode 0 x x 1 x0 101 111 cpi6 cpi5 cpi4 cpi3 cpi2 cpi1 3k? 5.1k ? 11k ? 0 0 0 1.06 0.625 0.289 0 0 1 2.12 1.25 0.580 0 1 0 3.18 1.875 0.870 0 1 1 4.24 2.5 1.160 1 0 0 5.30 3.125 1.450 1 0 1 6.36 3.75 1.730 1 1 0 7.42 4.375 2.020 1 1 1 8.50 5.0 2.320 tc4 tc3 tc2 tc1 00003 00017 00101 1 00111 5 01001 9 01012 3 01102 7 01113 1 10003 5 10013 9 10104 3 10114 7 11005 1 11015 5 11105 9 11116 3 f4 0 1 1 m3 m2 m1 000 001 010 011 100 101 110 111 f3 0 1 f2 0 1 f1 0 1 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) f1 pd1 m1 m2 m3 f3 p1 p2 cpi1 cpi2 cpi5 cpi6 tc4 pd2 f2 cpi3 cpi4 db21 tc3 tc2 tc1 db22 db23 f4 f5 f5 x 0 1 negative positive prescaler value power- down 2 current setting 2 current setting 1 timer counter control fastlock mode fastlock enable cp three- state muxout control power- down 1 counter reset control bits phase detector polarity counter operation normal r, a, b counters held in reset charge pump output normal three-state fastlock disabled fastlock mode 1 fastlock mode 2 fastlock mode three-state output digital lock detect (active high) n divider output dv dd r divider output n-channel open-drain lock detect serial data output dgnd output timeout (pfd cycles) i cp (ma) asynchronous power-down normal operation asynchronous power-down synchronous power-down ce pin prescaler value pd polarity 0 3338-025 figure 25. function latch map
adf4107 rev. a | page 15 of 20 initialization latch map p2 p1 00 8/9 0 1 16/17 1 0 32/33 1 1 64/65 pd2 pd1 mode 0 x x 1 x0 101 111 cpi6 cpi5 cpi4 cpi3 cpi2 cpi1 3k ? 5.1k ? 11k ? 0 0 0 1.06 0.625 0.289 0 0 1 2.12 1.25 0.580 0 1 0 3.18 1.875 0.870 0 1 1 4.24 2.5 1.160 1 0 0 5.30 3.125 1.450 1 0 1 6.36 3.75 1.730 1 1 0 7.42 4.375 2.020 1 1 1 8.50 5.0 2.320 tc4 tc3 tc2 tc1 00003 00017 00101 1 00111 5 01001 9 01012 3 01102 7 01113 1 10003 5 10013 9 10104 3 10114 7 11005 1 11015 5 11105 9 11116 3 f4 0 1 1 m3 m2 m1 000 001 010 011 100 101 110 111 f3 0 1 f2 0 1 f1 0 1 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (1) f1 pd1 m1 m2 m3 f3 p1p2 cpi1 cpi2 cpi5 cpi6 tc4 pd2 f2 cpi3 cpi4 db21 tc3 tc2 tc1 db22 db23 f4 f5 three-state f5 x 0 1 negative positive prescaler value power- down 2 current setting 2 current setting 1 timer counter control fastlock mode fastlock enable cp three- state muxout control power- down 1 counter reset control bits phase detector polarity counter operation normal r, a, b counters held in reset charge pump output normal fastlock disabled fastlock mode 1 fastlock mode 2 fastlock mode three-state output digital lock detect (active high) n divider output dv dd r divider output n-channel open-drain lock detect serial data output dgnd output timeout (pfd cycles) i cp (ma) asynchronous power-down normal operation asynchronous power-down synchronous power-down ce pin prescaler value pd polarity 0 3338-026 figure 26. initialization latch map
adf4107 rev. a | page 16 of 20 function latch the on-chip function latch is programmed with c2 and c1 set to 1 and 0, respectively. figure 25 shows the input data format for programming the function latch. counter reset db2 (f1) is the counter reset bit. when this bit is 1, the r counter and the ab counters are reset. for normal operation, this bit should be 0. upon powering up, the f1 bit needs to be disabled (set to 0). then, the n counter resumes counting in close alignment with the r counter. (the maximum error is one prescaler cycle). power-down db3 (pd1) and db21 (pd2) provide programmable power- down modes. they are enabled by the ce pin. when the ce pin is low, the device is immediately disabled regardless of the states of pd2 and pd1. in the programmed asynchronous power-down, the device powers down immediately after latching a 1 into the pd1 bit, with the condition that pd2 has been loaded with a 0. in the programmed synchronous power-down, the device power-down is gated by the charge pump to prevent unwanted frequency jumps. once the power-down is enabled by writing a 1 into pd1 (on condition that a 1 has also been loaded to pd2), then the device goes into power-down on the occurrence of the next charge pump event. when a power-down is activated (either in synchronous or asynchronous mode, including ce pin-activated power-down), the following events occur: ? all active dc current paths are removed. ? the r, n, and timeout counters are forced to their load state conditions. ? the charge pump is forced into three-state mode. ? the digital lock detect circuitry is reset. ? the rf in input is debiased. ? the reference input buffer circuitry is disabled. ? the input register remains active and capable of loading and latching data. muxout control the on-chip multiplexer is controlled by m3, m2, and m1 on the adf4107. figure 25 shows the truth table. fastlock enable bit db9 of the function latch is the fastlock enable bit. fastlock is enabled only when this bit is 1. fastlock mode bit db10 of the function latch is the fastlock mode bit. when fastlock is enabled, this bit determines which fastlock mode is used. if the fastlock mode bit is 0, then fastlock mode 1 is selected; and if the fastlock mode bit is 1, then fastlock mode 2 is selected. fastlock mode 1 the charge pump current is switched to the contents of current setting 2. the device enters fastlock by having a 1 written to the cp gain bit in the ab counter latch. the device exits fastlock by having a 0 written to the cp gain bit in the ab counter latch. fastlock mode 2 the charge pump current is switched to the contents of current setting 2. the device enters fastlock by having a 1 written to the cp gain bit in the ab counter latch. the device exits fastlock under the control of the timer counter. after the timeout period determined by the value in tc4 to tc1, the cp gain bit in the ab counter latch is automatically reset to 0 and the device reverts to normal mode instead of fastlock. see figure 25 for the timeout periods. timer counter control the user has the option of programming two charge pump currents. the intent is that current setting 1 is used when the rf output is stable and the system is in a static state. current setting 2 is meant to be used when the system is dynamic and in a state of change (that is, when a new output frequency is programmed). the normal sequence of events is as follows: the user initially decides what the preferred charge pump currents are going to be. for example, the choice may be 2.5 ma as current setting 1 and 5 ma as current setting 2. at the same time it must be decided how long the secondary current is to stay active before reverting to the primary current. this is controlled by the timer counter control bits, db14 to db11 (tc4 to tc1), in the function latch. the truth table is given in figure 25 . to program a new output frequency, the user simply programs the ab counter latch with new values for a and b. at the same time, the cp gain bit can be set to 1, which sets the charge pump with the value in cpi6 to cpi4 for a period of time determined by tc4 to tc1. when this time is up, the charge pump current reverts to the value set by cpi3 to cpi1. at the same time the cp gain bit in the ab counter latch is reset to 0 and is ready for the next time that the user wishes to change the frequency. note that there is an enable feature on the timer counter. it is enabled when fastlock mode 2 is chosen by setting the fastlock mode bit (db10) in the function latch to 1.
adf4107 rev. a | page 17 of 20 charge pump currents cpi3, cpi2, and cpi1 program current setting 1 for the charge pump. cpi6, cpi5, and cpi4 program current setting 2 for the charge pump. the truth table is given in figure 25 . prescaler value p2 and p1 in the function latch set the prescaler values. the prescaler value should be chosen so that the prescaler output frequency is always less than or equal to 300 mhz. thus, with an rf frequency of 4 ghz, a prescaler value of 16/17 is valid but a value of 8/9 is not valid. pd polarity this bit sets the phase detector polarity bit. see figure 25 . cp three-state this bit controls the cp output pin. with the bit set high, the cp output is put into three-state. with the bit set low, the cp output is enabled. initialization latch the initialization latch is programmed when c2 and c1 are set to 1 and 1. this is essentially the same as the function latch (programmed when c2, c1 = 1, 0). however, when the initialization latch is programmed an additional internal reset pulse is applied to the r and ab counters. this pulse ensures that the ab counter is at load point when the ab counter data is latched and the device will begin counting in close phase alignment. if the latch is programmed for synchronous power-down (ce pin is high; pd1 bit is high; pd2 bit is low), the internal pulse also triggers this power-down. the prescaler reference and the oscillator input buffer are unaffected by the internal reset pulse and so close phase alignment is maintained when counting resumes. when the first ab counter data is latched after initialization, the internal reset pulse is again activated. however, successive ab counter loads after this will not trigger the internal reset pulse. device programming after initial power-up after initially powering up the device, there are three ways to program the device. initialization latch method 1. apply v dd . 2. program the initialization latch (11 in two lsbs of input word). make sure that the f1 bit is programmed to 0. 3. next, do a function latch load (10 in two lsbs of the control word), making sure that the f1 bit is programmed to a 0. 4. then do an r load (00 in two lsbs). 5. then do an ab load (01 in two lsbs). 6. when the initialization latch is loaded, the following occurs: a. the function latch contents are loaded. b. an internal pulse resets the r, ab, and timeout counters to load-state conditions and also three-states the charge pump. note that the prescaler band gap reference and the oscillator input buffer are unaffected by the internal reset pulse, allowing close phase alignment when counting resumes. c. latching the first ab counter data after the initialization word activates the same internal reset pulse. successive ab loads do not trigger the internal reset pulse unless there is another initialization. ce pin method 1. apply v dd . 2. bring ce low to put the device into power-down. this is an asychronous power-down in that it happens immediately. 3. program the function latch (10). 4. program the r counter latch (00). 5. program the ab counter latch (01). 6. bring ce high to take the device out of power-down. the r and ab counters resume counting in close alignment. note that after ce goes high, a duration of 1 s may be required for the prescaler band gap voltage and oscillator input buffer bias to reach steady state. ce can be used to power the device up and down in order to check for channel activity. the input register does not need to be reprogrammed each time the device is disabled and enabled as long as it has been programmed at least once after v dd was initially applied. counter reset method 1. apply v dd . 2. do a function latch load (10 in two lsbs). as part of this, load 1 to the f1 bit. this enables the counter reset. 3. do an r counter load (00 in two lsbs). 4. do an ab counter load (01 in two lsbs). 5. do a function latch load (10 in two lsbs). as part of this, load 0 to the f1 bit. this disables the counter reset. this sequence provides the same close alignment as the initialization method. it offers direct control over the internal reset. note that counter reset holds the counters at load point and three-states the charge pump, but does not trigger synchronous power-down.
adf4107 rev. a | page 18 of 20 applications local oscillator for lmds base station transmitter figure 27 shows the adf4107 being used with a vco to produce the lo for an lmds base station. the reference input signal is applied to the circuit at fref in and, in this case, is terminated in 50 . a typical base station system has either a tcxo or an ocxo driving the reference input without any 50 termination. to have a channel spacing of 1 mhz at the output, the 10 mhz reference input must be divided by 10, using the on-chip reference divider of the adf4107. the charge pump output of the adf4107 (pin 2) drives the loop filter. in calculating the loop filter component values, a number of items need to be considered. in this example, the loop filter was designed so that the overall phase margin for the system would be 45. other pll system specifications are: k d = 5.0 ma k v = 80 mhz/v loop bandwidth = 70 khz f pfd = 1 mhz n = 6300 extra reference spur attenuation = 10 db all of these specifications are needed and used to derive the loop filter component values shown in figure 27. figure 27 gives a typical phase noise performance of ?83 dbc/hz at 1 khz offset from the carrier. spurs are better than ?70 dbc. the loop filter output drives the vco, which, in turn, is fed back to the rf input of the pll synthesizer and also drives the rf output terminal. a t-circuit configuration provides 50 matching between the vco output, the rf output, and the rf in terminal of the synthesizer. in a pll system, it is important to know when the system is in lock. in figure 27, this is accomplished by using the muxout signal from the synthesizer. the muxout pin can be programmed to monitor various internal signals in the synthesizer. one of these is the ld or lock detect signal. adf4107 ce clk data le 1000pf 1000pf ref in 100pf cp muxout cpgnd agnd dgnd 100pf 820pf 47pf 100pf 51 ? 1.7k ? 7.5k ? 100pf 18 ? notes: 1. decoupling capacitors (0.1f/10pf) on av dd , dv dd , and v p of the adf4106 and on v cc of the v956me03 have been omitted from the diagram to aid clarity. spi ? -compatible serial bus r set rf in a rf in b av dd dv dd v p fref in v dd v p lock detect v cc v956me01 1, 3, 4, 5, 7, 8, 9, 11, 12, 13 18 ? 18 ? 100pf rf ou t 5.1k ? 7 15 16 8 2 14 6 5 1 9 4 3 14 2 10 51 ? 03338-027 figure 27. 6.3 ghz local oscillator using the adf4107
adf4107 rev. a | page 19 of 20 interfacing the adf4107 has a simple spi?-compatible serial interface for writing to the device. clk, data, and le control the data transfer. when le (latch enable) goes high, the 24 bits that have been clocked into the input register on each rising edge of clk are transferred to the appropriate latch. see figure 2 for the timing diagram and table 5 for the latch truth table. the maximum allowable serial clock rate is 20 mhz. this means that the maximum update rate possible for the device is 833 khz or one update every 1.2 s. this is certainly more than adequate for systems that have typical lock times in hundreds of microseconds. aduc812 interface figure 28 shows the interface between the adf4107 and the aduc812 microconverter?. since the aduc812 is based on an 8051 core, this interface can be used with any 8051-based microcontroller. the microconverter is set up for spi master mode with cpha = 0. to initiate the operation, the i/o port driving le is brought low. each latch of the adf4107 needs a 24-bit word. this is accomplished by writing three 8-bit bytes from the microconverter to the device. when the third byte has been written, the le input should be brought high to complete the transfer. on first applying power to the adf4107, it needs four writes (one each to the initialization latch, function latch, r counter latch, and n counter latch) for the output to become active. i/o port lines on the aduc812 are also used to control power- down (ce input) and to detect lock (muxout configured as lock detect and polled by the port input). when operating in the mode described, the maximum sclock rate of the aduc812 is 4 mhz. this means that the maximum rate at which the output frequency can be changed is 166 khz. clk data le ce muxout (lock detect) mosi adf4107 sclock i/o ports aduc812 03338-028 figure 28. aduc812 to adf4107 interface adsp-2181 interface figure 29 shows the interface between the adf4107 and the adsp21xx digital signal processor. the adf4107 needs a 24-bit serial word for each latch write. the easiest way to accomplish this using the adsp-21xx family is to use the autobuffered transmit mode of operation with alternate framing. this provides a means for transmitting an entire block of serial data before an interrupt is generated. set up the word length for 8 bits and use three memory locations for each 24-bit word. to program each 24-bit latch, store the three 8-bit bytes, enable the autobuffered mode, and then write to the transmit register of the dsp. this last operation initiates the autobuffer transfer. clk data le ce muxout (lock detect) dt adf4107 sclock i/o flags adsp-21xx tfs 03338-029 figure 29. adsp-21xx to adf4107 interface pcb design guidelines for chip scale package the lands on the chip scale package (cp-20) are rectangular. the printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. the land should be centered on the pad. this ensures that the solder joint size is maximized. the bottom of the chip scale package has a central thermal pad. the thermal pad on the printed circuit board should be at least as large as this exposed pad. on the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. this ensures that shorting is avoided. thermal vias may be used on the printed circuit board thermal pad to improve thermal performance of the package. if vias are used, they should be incorporated in the thermal pad at 1.2 mm pitch grid. the via diameter should be between 0.3 mm and 0.33 mm and the via barrel should be plated with 1 oz. copper to plug the via. the user should connect the printed circuit board thermal pad to agnd.
adf4107 rev. a | page 20 of 20 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 30. 16-lead thin shrink small outline package [tssop] (ru-16)dimensions shown in millimeters 1 20 5 6 11 16 15 10 2.25 2.10 sq 1.95 0.75 0.55 0.35 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 0.05 max 0.02 nom 1.00 0.85 0.80 seating plane pin 1 indicato r top view 3.75 bcs sq 4.00 bsc sq coplanarity 0.08 0.60 max 0.60 max 0.25 min compliant to jedec standards mo-220-vggd-1 pin 1 indicator figure 31. 20-lead lead frame chip scale package [lfcsp_vq] 4 mm x 4 mm body, very thin quad (cp-20-1) dimensions shown in millimeters ordering guide model temperature range package description package option adf4107bru C40c to + 85c 16-lead thin shrink small outline package [tssop] ru-16 adf4107bru-reel C40c to + 85c 16-lead thin shrink small outline package [tssop] ru-16 adf4107bru-reel7 C40c to + 85c 16-lead thin shrink small outline package [tssop] ru-16 adf4107bruz 1 C40c to + 85c 16-lead thin shrink small outline package [tssop] ru-16 adf4107bruz-reel 1 C40c to + 85c 16-lead thin shrink small outline package [tssop] ru-16 ADF4107BRUZ-REEL7 1 C40c to + 85c 16-lead thin shrink small outline package [tssop] ru-16 adf4107bcp C40c to + 85c 20-lead lead frame chip scale package [lfcsp_vq] cp-20-1 adf4107bcp-reel C40c to + 85c 20-lead lead frame chip scale package [lfcsp_vq] cp-20-1 adf4107bcp-reel7 C40c to + 85c 20-lead lead frame chip scale package [lfcsp_vq] cp-20-1 adf4107bcpz 1 C40c to + 85c 20-lead lead frame chip scale package [lfcsp_vq] cp-20-1 adf4107bcpz-reel 1 C40c to + 85c 20-lead lead frame chip scale package [lfcsp_vq] cp-20-1 adf4107bcpz-reel7 1 C40c to + 85c 20-lead lead frame chip scale package [lfcsp_vq] cp-20-1 1 z = rohs compliant part. ?2003-2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. c03338-0-4/07(a)

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